US 11,792,753 B2
Synchronization signal block time domain pattern design
Jing Sun, San Diego, CA (US); Xiaoxia Zhang, San Diego, CA (US); Tao Luo, San Diego, CA (US); and Juan Montojo, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 24, 2021, as Appl. No. 17/183,982.
Claims priority of provisional application 62/990,373, filed on Mar. 16, 2020.
Prior Publication US 2021/0289454 A1, Sep. 16, 2021
Int. Cl. H04W 56/00 (2009.01); H04W 76/20 (2018.01); H04W 76/10 (2018.01)
CPC H04W 56/001 (2013.01) [H04W 76/10 (2018.02); H04W 76/20 (2018.02)] 26 Claims
OG exemplary drawing
 
1. A method for wireless communication at a user equipment (UE), comprising:
identifying, based at least in part on a sub-carrier spacing configuration and a frequency band of a network device, a synchronization signal block configuration used to communicate synchronization signal blocks, wherein the synchronization signal block configuration defines a placement of control symbols within a slot, a first set of synchronization signal blocks beginning at a symbol two of the slot and spanning a first set of symbols of the slot, and a second set of synchronization signal blocks beginning at a symbol nine of the slot and spanning a second set of symbols of the slot;
monitoring a set of resources in the frequency band according to the synchronization signal block configuration;
receiving the synchronization signal blocks based at least in part on the monitoring, the synchronization signal blocks comprising the first set of synchronization signal blocks or the second set of synchronization signal blocks or both; and
establishing or modifying a connection with the network device based at least in part on the received synchronization signal blocks.