CPC H04N 19/124 (2014.11) [H04N 19/103 (2014.11); H04N 19/96 (2014.11)] | 20 Claims |
1. A video processor comprising:
a memory configured to receive a video frame having a plurality of rows of coding tree units (CTUs);
a bus;
a first video processing engine coupled to the bus;
a second video processing engine coupled to the bus; and
a controller coupled to the bus, wherein the controller is configured to assign a first row of the plurality of rows to the first video processing engine and a second row of the plurality of rows to the second video processing engine;
wherein the first video processing engine is configured to:
determine a first estimated quantization parameter (QP) for the first row; and
encode a first CTU of the first row; and
wherein the second video processing engine is configured to:
determine a second estimated QP for the second row;
receive the first estimated QP;
determine a running QP for the second row based on the first estimated QP; and
encode a second CTU of the second row.
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