CPC H04L 63/0869 (2013.01) [H04L 9/0852 (2013.01); H04L 9/3242 (2013.01); H04L 9/3265 (2013.01)] | 14 Claims |
1. An apparatus, comprising:
a hardware processor to:
store two cryptographic representations of a trust relationship between a first device and a second device, the two cryptographic representations based on two pairs of asymmetric hash-based multi-time signature keys;
receive an attestation request message from the second device, the attestation request message comprising attestation request data and a memory address for the first device from the second device and a hash-based multi-time signature generated by the second device; and
in response to receiving the attestation request message, to:
verify the attestation request data;
validate the memory address for the first device;
verify the hash-based multi-time signature generated by the second device using a public key associated with the second device;
generate an attestation reply message using a hash-based multi-time private signature key; and
send the attestation reply message to the second device.
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