CPC H04L 9/3093 (2013.01) [H04L 2209/12 (2013.01)] | 21 Claims |
1. A hardware processor, comprising:
fetch circuitry to fetch an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers;
decode circuitry to decode the decoded butterfly instruction to generate a decoded butterfly instruction; and
execution circuitry to execute the decoded butterfly instruction to:
retrieve operands representing a first input polynomial from the first source, a second input polynomial from the second source, and a primitive nth root of unity from the third source;
perform, in an atomic fashion, a butterfly operation to generate a first output and a second output; and
store the first output and the second output in a register file accessible to the execution circuitry.
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