US 11,792,005 B2
Processor hardware and instructions for lattice based cryptography
Santosh Ghosh, Hillsboro, OR (US); Andrew H. Reinders, Portland, OR (US); and Manoj Sastry, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Clara, CA (US)
Filed on Mar. 21, 2022, as Appl. No. 17/699,830.
Prior Publication US 2022/0247561 A1, Aug. 4, 2022
Int. Cl. H04L 9/40 (2022.01); H04L 9/30 (2006.01)
CPC H04L 9/3093 (2013.01) [H04L 2209/12 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A hardware processor, comprising:
fetch circuitry to fetch an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers;
decode circuitry to decode the decoded butterfly instruction to generate a decoded butterfly instruction; and
execution circuitry to execute the decoded butterfly instruction to:
retrieve operands representing a first input polynomial from the first source, a second input polynomial from the second source, and a primitive nth root of unity from the third source;
perform, in an atomic fashion, a butterfly operation to generate a first output and a second output; and
store the first output and the second output in a register file accessible to the execution circuitry.