US 11,792,004 B2
Polynomial multiplication for side-channel protection in cryptography
Santosh Ghosh, Hillsboro, OR (US); and Manoj Sastry, Portland, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 17, 2021, as Appl. No. 17/478,579.
Prior Publication US 2023/0091951 A1, Mar. 23, 2023
Int. Cl. H04L 9/30 (2006.01); G06F 7/487 (2006.01); G06F 7/53 (2006.01); H04L 9/08 (2006.01)
CPC H04L 9/3026 (2013.01) [G06F 7/4876 (2013.01); G06F 7/53 (2013.01); H04L 9/0869 (2013.01); H04L 9/3093 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more processors to process data; and
polynomial multiplier circuitry, the polynomial multiplier circuitry including one or more sets of multiplier circuits;
wherein the one or more processors are to perform a cryptographic key operation utilizing the polynomial multiplier circuitry, the cryptographic key operation including processing a first plurality of coefficient values representing a first polynomial and a second plurality of coefficient values representing a second polynomial, wherein the polynomial multiplier circuitry is to:
select a first set of one or more coefficient values of the first plurality of coefficient values for processing;
perform a set of multiplication operations to multiply each of the first set of one or more coefficient values by all of the second plurality of coefficient values in parallel using the one or more sets of multiplier circuits; and
iteratively perform sets of multiplication operations to multiply additional sets of one or more coefficient values of the first set of coefficient values with all of the second plurality of coefficient values in parallel using the one or more sets of multiplier circuits until all of the first plurality of coefficient values are processed.