US 11,791,934 B2
Communication device, communication method, program, and communication system
Hiroo Takahashi, Kanagawa (JP); Takashi Yokokawa, Kanagawa (JP); Sonfun Lee, Kanagawa (JP); and Naohiro Koshisaka, Kanagawa (JP)
Assigned to Sony Group Corporation, Tokyo (JP)
Appl. No. 16/92,240
Filed by Sony Group Corporation, Tokyo (JP)
PCT Filed May 2, 2017, PCT No. PCT/JP2017/017221
§ 371(c)(1), (2) Date Oct. 9, 2018,
PCT Pub. No. WO2017/199761, PCT Pub. Date Nov. 23, 2017.
Claims priority of application No. 2016-099955 (JP), filed on May 18, 2016.
Prior Publication US 2019/0097757 A1, Mar. 28, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 1/00 (2006.01); G06F 13/42 (2006.01); G06F 11/10 (2006.01); G06F 1/10 (2006.01); G06F 13/20 (2006.01); H04L 7/04 (2006.01); H04L 1/08 (2006.01)
CPC H04L 1/0061 (2013.01) [G06F 1/10 (2013.01); G06F 11/1004 (2013.01); G06F 13/20 (2013.01); G06F 13/4291 (2013.01); H04L 1/0041 (2013.01); G06F 11/1032 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0016 (2013.01); H04L 1/08 (2013.01); H04L 7/041 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A communication device, comprising:
transmission and reception circuitry configured to perform a communication with an external communication device, the communication including transmitting and receiving data via a data signal line and transmitting a clock via a clock signal line; and
control circuitry configured to
transmit a command giving an instruction to enter a predetermined data rate mode,
thereafter, detect an occurrence of an error in a signal by comparing a first bit sequence following a preamble of the data received to a second bit sequence corresponding to a data type designated by the preamble, and
in a case where the occurrence of the error is detected, cause the transmission and reception circuitry to transmit the clock via the clock signal line for a first duration corresponding to at least a predetermined number of bits following the preamble,
wherein when the preamble of the data specifies transmission of a cyclic redundancy check (CRC) word, the CRC word including a token and a CRC-5, and the control circuitry detects an occurrence of at least one of a token error or a CRC error on the basis of the first bit sequence, the transmission and reception circuitry transmits a command signal after transmitting the clock for a second duration, the second duration corresponding to at least a number of bits in the CRC word.