US 11,791,926 B2
Efficiently interconnecting a plurality of computing nodes to form a circuit-switched network
Hitesh Ballani, Cambridge (GB); Christian L. Belady, Mercer Island, WA (US); Lisa Ru-Feng Hsu, Durham, NC (US); Winston Allen Saunders, Seattle, WA (US); Paolo Costa, London (GB); Douglas M. Carmean, Seattle, WA (US); Kai Shi, Cambridge (GB); and Charles Boecker, Redmond, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Dec. 22, 2022, as Appl. No. 18/87,429.
Application 18/087,429 is a continuation of application No. 17/173,052, filed on Feb. 10, 2021, granted, now 11,539,453.
Claims priority of provisional application 63/109,276, filed on Nov. 3, 2020.
Prior Publication US 2023/0125673 A1, Apr. 27, 2023
Int. Cl. H04B 10/00 (2013.01); H04J 14/02 (2006.01); H04J 14/00 (2006.01)
CPC H04J 14/0267 (2013.01) [H04J 14/0212 (2013.01); H04J 14/0223 (2013.01); H04J 14/0241 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for configuring a communication path between a source computing node and a destination computing node in a multi-stage network of circuit switches, the method comprising:
identifying a first circuit switch from a first network stage, the first network stage including a plurality of optical circuit switches;
identifying a second circuit switch from a second network stage, the second network stage including a plurality of electrical circuit switches; and
scheduling communication of data from the source computing node to the destination computing node via the first circuit switch and the second circuit switch.