CPC H04B 7/086 (2013.01) [H04B 7/068 (2013.01); H04B 7/0684 (2013.01); H04B 7/0851 (2013.01); H04L 1/0001 (2013.01); H04L 5/0033 (2013.01); H04L 5/0035 (2013.01); H04L 5/0042 (2013.01); H04L 5/0051 (2013.01); H04L 5/0073 (2013.01); H04L 5/0094 (2013.01); H04L 25/0226 (2013.01); H04L 27/2646 (2013.01); H04W 52/325 (2013.01); H04W 72/23 (2023.01); H04B 7/0452 (2013.01); H04L 1/0003 (2013.01); H04L 1/0009 (2013.01); H04L 5/0007 (2013.01); H04L 5/0026 (2013.01)] | 10 Claims |
1. An integrated circuit comprising:
reception circuitry, which, in operation, controls receiving a Demodulation Reference Signal (DMRS) and receiving downlink control information indicating a mapping pattern of the DMRS from a plurality of mapping patterns; and
determination circuitry, which, in operation, controls determining the mapping pattern based on the downlink control information,
wherein the plurality of mapping patterns includes a first mapping pattern and a second mapping pattern,
wherein resource elements used for the DMRS of the second mapping pattern are same as a part of resource elements used for the DMRS of the first mapping pattern, and
wherein a number of the resource elements used for the DMRS of the first mapping pattern is larger than a number of the resource elements used for the DMRS of the second mapping pattern.
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