US 11,791,838 B2
Near-storage acceleration of dictionary decoding
Sahand Salamat, San Diego, CA (US); Joo Hwan Lee, San Jose, CA (US); Armin Haj Aboutalebi, San Jose, CA (US); Praveen Krishnamoorthy, Fremont, CA (US); Xiaodong Zhao, Cupertino, CA (US); Hui Zhang, San Jose, CA (US); and Yang Seok Ki, Palo Alto, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 24, 2021, as Appl. No. 17/357,953.
Claims priority of provisional application 63/138,165, filed on Jan. 15, 2021.
Prior Publication US 2022/0231698 A1, Jul. 21, 2022
Int. Cl. H03M 7/30 (2006.01); G06F 3/06 (2006.01)
CPC H03M 7/3088 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0644 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An accelerator, comprising:
a memory configured to store a dictionary table;
an address generator configured to generate an address in the dictionary table in the memory based at least in part on an encoded value, the encoded value with an encoded width; and
an output filter configured to filter a decoded value from an entry in the dictionary table based at least in part on a starting location within the entry, the entry including the decoded value and at least a first part of a second decoded value, the entry and the starting location identified based at least in part on the address, the decoded value with a decoded width,
wherein the accelerator is configured to support at least two different encoded widths.