US 11,791,779 B2
Analog circuit differential pair element mismatch detection using spectral separation
Ramin Zanbaghi, Austin, TX (US); John L. Melanson, Austin, TX (US); and Edmund M. Schneider, Austin, TX (US)
Assigned to Cirrus Logic, Inc., Austin, TX (US)
Filed by Cirrus Logic International Semiconductor Ltd., Edinburgh (GB)
Filed on Dec. 11, 2020, as Appl. No. 17/119,228.
Prior Publication US 2022/0190789 A1, Jun. 16, 2022
Int. Cl. H03M 1/12 (2006.01); H03F 1/56 (2006.01); H03F 3/45 (2006.01)
CPC H03F 1/56 (2013.01) [H03F 3/45475 (2013.01); H03M 1/12 (2013.01); H03F 2200/129 (2013.01); H03F 2203/45116 (2013.01)] 24 Claims
OG exemplary drawing
 
14. An apparatus, comprising:
an analog circuit having a plurality of differential pairs of elements, wherein for each pair of the plurality of differential pairs of elements, the elements of the pair are designed to match but may have mismatch that induces error;
an analog-to-digital converter (ADC) configured to monitor an output of the analog circuit; and
a controller configured to, for each pair of at least two pairs of the plurality of differential pairs of elements:
spectrally separate the mismatch-induced error of the pair from mismatch-induced error of a remainder of the plurality of differential pairs of elements; and
analyze the monitored output to measure the mismatch-induced error of the pair.