	US 11,791,417 B2
	Semiconductor device and manufacturing method thereof
Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Aug. 16, 2021, as Appl. No. 17/402,722.
Application 17/223,278 is a division of application No. 15/973,835, filed on May 8, 2018, granted, now 11,211,499.
Application 17/402,722 is a continuation of application No. 17/223,278, filed on Apr. 6, 2021, granted, now 11,183,597.
Application 15/973,835 is a continuation of application No. 12/880,259, filed on Sep. 13, 2010, abandoned.
Claims priority of application No. 2009-214485 (JP), filed on Sep. 16, 2009.
Prior Publication US 2021/0376152 A1, Dec. 2, 2021
Int. Cl. H01L 29/786 (2006.01); H01L 27/12 (2006.01)

CPC H01L 29/7869 (2013.01) [H01L 27/1225 (2013.01); H01L 2924/0002 (2013.01)]

15 Claims

1. A semiconductor device comprising:

a gate electrode layer;

a nitride insulating film over and in direct contact with the gate electrode layer;

an oxide insulating film over and in direct contact with the nitride insulating film;

an oxide semiconductor layer over and in direct contact with the oxide insulating film, the oxide semiconductor layer comprising a channel formation region;

a first insulating layer over and in direct contact with the oxide semiconductor layer;

a first wiring layer in electrical contact with the oxide semiconductor layer;

a second wiring layer over and in contact with the first wiring layer;

a second insulating layer over the first insulating layer;

a third insulating layer over the second insulating layer;

a color filter layer between the second insulating layer and the third insulating layer; and

a first electrode of a light-emitting element over the third insulating layer,

wherein the first wiring layer and the second wiring layer are electrically connected to the oxide semiconductor layer through a first opening of the first insulating layer,

wherein the first electrode of the light-emitting element is electrically connected to the second wiring layer through a second opening of the second insulating layer and a third opening of the third insulating layer,

wherein the channel formation region of the oxide semiconductor layer comprises a crystalline portion,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the first wiring layer comprises molybdenum,

wherein the second wiring layer comprises copper, and

wherein the gate electrode layer is a stacked-layer structure and comprises copper.