US 11,791,377 B2
Power device integration on a common substrate
Jacek Korec, Cape Haze, FL (US); and Boyi Yang, San Jose, CA (US)
Assigned to Silanna Asia Pte Ltd, Singapore (SG)
Filed by Silanna Asia Pte Ltd, Singapore (SG)
Filed on Mar. 17, 2022, as Appl. No. 17/655,336.
Application 15/808,029 is a division of application No. 15/228,213, filed on Aug. 4, 2016, granted, now 9,825,124, issued on Nov. 21, 2017.
Application 17/655,336 is a continuation of application No. 16/387,243, filed on Apr. 17, 2019, granted, now 11,302,775.
Application 16/387,243 is a continuation of application No. 15/808,029, filed on Nov. 9, 2017, granted, now 10,290,703, issued on May 14, 2019.
Application 15/228,213 is a continuation of application No. 13/939,451, filed on Jul. 11, 2013, granted, now 9,412,881, issued on Aug. 9, 2016.
Application 13/939,451 is a continuation in part of application No. 13/887,704, filed on May 6, 2013, granted, now 8,994,105, issued on Mar. 31, 2015.
Claims priority of provisional application 61/677,660, filed on Jul. 31, 2012.
Prior Publication US 2022/0208964 A1, Jun. 30, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 27/06 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/94 (2006.01); H01L 29/36 (2006.01); H01L 29/861 (2006.01); H01L 29/417 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/73 (2006.01); H01L 29/735 (2006.01); H01L 29/8605 (2006.01); H01L 29/872 (2006.01); H01L 21/8249 (2006.01)
CPC H01L 29/0626 (2013.01) [H01L 21/8249 (2013.01); H01L 21/823437 (2013.01); H01L 27/0629 (2013.01); H01L 27/0635 (2013.01); H01L 27/088 (2013.01); H01L 29/1083 (2013.01); H01L 29/1087 (2013.01); H01L 29/1095 (2013.01); H01L 29/36 (2013.01); H01L 29/402 (2013.01); H01L 29/42304 (2013.01); H01L 29/4933 (2013.01); H01L 29/66181 (2013.01); H01L 29/66704 (2013.01); H01L 29/7302 (2013.01); H01L 29/735 (2013.01); H01L 29/78 (2013.01); H01L 29/7825 (2013.01); H01L 29/861 (2013.01); H01L 29/8605 (2013.01); H01L 29/872 (2013.01); H01L 29/94 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/66696 (2013.01); H01L 29/7821 (2013.01); H01L 29/7824 (2013.01); H01L 29/7835 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/11 (2013.01); H01L 2224/13 (2013.01); H01L 2924/00 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising at least one metal-oxide-semiconductor field-effect transistor (MOSFET) power device, the semiconductor structure comprising:
an active region;
a buried well having a first conductivity type formed in the active region;
a source region having a second conductivity type formed in the active region proximate an upper surface of the active region, the source region being electrically connected to the buried well;
a drain region having the second conductivity type formed in the active region proximate the upper surface of the active region and spaced laterally from the source region;
a body region having the first conductivity type formed in the active region between the source region and the drain region, the body region being formed in direct contact on at least a portion of the buried well;
a gate formed above the active region proximate the upper surface of the active region, wherein the gate is electrically isolated from the active region by a gate insulating layer;
a drain terminal formed on the upper surface of the active region and electrically connected to the drain region;
a source terminal electrically connected to the source region;
a gate terminal electrically connected to the gate; and
a shielding structure formed proximate the upper surface of the active region between the gate and the drain region, wherein the shielding structure comprises a field plate configured to control an electric field distribution along a top oxide interface away from an edge of the gate nearest the drain terminal;
wherein the buried well has a first end below the source terminal and a second end that extends partially below the drain region, the second end being laterally spaced from the drain terminal between the drain terminal and the body region; and
wherein the buried well is configured, in conjunction with the drain region, to form a clamping diode operative to position a breakdown avalanche region between the buried well and the drain terminal.