US 11,791,375 B2
Capacitor architectures in semiconductor devices
Sudipto Naskar, Portland, OR (US); Manish Chandhok, Beaverton, OR (US); Abhishek A. Sharma, Portland, OR (US); Roman Caudillo, Portland, OR (US); Scott B. Clendenning, Portland, OR (US); and Cheyun Lin, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 19, 2022, as Appl. No. 17/578,839.
Application 17/578,043 is a division of application No. 16/828,497, filed on Mar. 24, 2020, granted, now 11,264,449.
Application 17/578,839 is a continuation of application No. 17/578,043, filed on Jan. 18, 2022.
Prior Publication US 2022/0140069 A1, May 5, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01)
CPC H01L 28/87 (2013.01) [H10B 12/033 (2023.02); H10B 12/31 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a pole;
a first disc electrode surrounding and in contact with a first portion of the pole;
a second disc electrode surrounding and in contact with a second portion of the pole, the second disc electrode over and spaced apart from the first disc electrode;
a dielectric layer surrounding and continuous between the first disc electrode and the second disc electrode, the dielectric layer along the pole between the first disc electrode and the second disc electrode; and
an electrode layer surrounding the dielectric layer, the electrode layer along the pole between the first disc electrode and the second disc electrode.