US 11,791,371 B2
Resistor structure
Chih-Fan Huang, Kaohsiung (TW); Hsiang-Ku Shen, Hsinchu (TW); Dian-Hau Chen, Hsinchu (TW); and Yen-Ming Chen, Chu-Pei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/460,564.
Prior Publication US 2023/0064385 A1, Mar. 2, 2023
Int. Cl. H01L 21/285 (2006.01); H01L 49/02 (2006.01); H01L 27/06 (2006.01); H01L 27/10 (2006.01); H01L 27/07 (2006.01); H01L 21/321 (2006.01)
CPC H01L 28/24 (2013.01) [H01L 21/28531 (2013.01); H01L 27/0676 (2013.01); H01L 27/0682 (2013.01); H01L 27/0794 (2013.01); H01L 27/101 (2013.01); H01L 21/3212 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a conductive feature and a first conductive plate over a substrate;
conformally depositing a dielectric layer over the conductive feature and the first conductive plate;
conformally depositing a conductive layer over the conductive feature and the first conductive plate; and
patterning the conductive layer to form a second conductive plate over the first conductive plate and a conductive line extending along a sidewall of the conductive feature.