US 11,791,359 B2
Light detecting element and method of manufacturing same
Yusuke Otake, Kanagawa (JP); and Toshifumi Wakano, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Jan. 19, 2022, as Appl. No. 17/579,391.
Application 17/579,391 is a continuation of application No. 16/463,760, granted, now 11,264,420, previously published as PCT/JP2018/040660, filed on Nov. 1, 2018.
Claims priority of application No. 2017-219685 (JP), filed on Nov. 15, 2017.
Prior Publication US 2022/0149090 A1, May 12, 2022
Int. Cl. H01L 27/146 (2006.01); H04N 25/75 (2023.01); H04N 25/77 (2023.01); H04N 25/79 (2023.01)
CPC H01L 27/1463 (2013.01) [H01L 27/14623 (2013.01); H01L 27/14627 (2013.01); H01L 27/14643 (2013.01); H01L 27/14689 (2013.01); H04N 25/75 (2023.01); H04N 25/77 (2023.01); H04N 25/79 (2023.01)] 17 Claims
OG exemplary drawing
 
1. A light detecting element comprising:
a substrate; and
a plurality of pixels arranged in a form of a matrix, the plurality of pixels each including:
a first semiconductor layer of a first conductivity type, the first semiconductor layer being formed in an outer peripheral portion in a vicinity of a pixel boundary;
a second semiconductor layer of a second conductivity type opposite from the first conductivity type, the second semiconductor layer being formed on an inside of the first semiconductor layer;
a third semiconductor layer of the second conductivity type on an inside of the second semiconductor layer in a plan view, the third semiconductor layer having a lower impurity concentration than the second semiconductor layer;
a fourth semiconductor layer of low impurity concentration and of the first conductivity type or the second conductivity type, the fourth semiconductor layer being adjacent to the second semiconductor layer in a depth direction of the substrate;
a fifth semiconductor layer of the first conductivity type, the fifth semiconductor layer being adjacent to the second semiconductor layer and being in a front surface of the substrate; and
an on-chip lens (OCL) on a light incident surface.