US 11,791,327 B2
Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
Kwang-Ho Kim, Pleasanton, CA (US); Masaaki Higashitani, Cupertino, CA (US); Fumiaki Toyama, Cupertino, CA (US); and Akio Nishida, Yokkaichi (JP)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Aug. 25, 2021, as Appl. No. 17/411,635.
Application 17/411,635 is a continuation of application No. 16/669,888, filed on Oct. 31, 2019, granted, now 11,133,297.
Application 16/669,888 is a continuation of application No. 16/243,469, filed on Jan. 9, 2019, granted, now 10,510,738, issued on Dec. 17, 2019.
Application 16/243,469 is a continuation in part of application No. 15/873,101, filed on Jan. 17, 2018, granted, now 10,283,493, issued on May 7, 2019.
Prior Publication US 2022/0013518 A1, Jan. 13, 2022
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/8083 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/41 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first die comprising a three-dimensional memory device including a three-dimensional array of NAND memory elements; and
a second die comprising a semiconductor substrate, a peripheral logic circuitry that includes complementary metal oxide semiconductor (CMOS) devices located on the semiconductor substrate, and a through-substrate via structure that vertically extends through the semiconductor substrate and having a vertical extent that is not less than a thickness of the semiconductor substrate;
wherein:
the first die is bonded to the second die; and
gate structures of the CMOS devices of the second die are located between the three-dimensional array of NAND memory elements of the first die and the semiconductor substrate of the second die containing active regions separated by a channel of the CMOS devices.