US 11,791,303 B2
Semiconductor package including semiconductor chips
Hyungu Kang, Hwaseong-si (KR); and Jaekyu Sung, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 19, 2023, as Appl. No. 18/99,092.
Application 18/099,092 is a continuation of application No. 17/223,614, filed on Apr. 6, 2021, granted, now 11,569,193.
Claims priority of application No. 10-2020-0139250 (KR), filed on Oct. 26, 2020.
Prior Publication US 2023/0154886 A1, May 18, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 23/498 (2006.01)
CPC H01L 24/73 (2013.01) [H01L 23/49816 (2013.01); H01L 24/06 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 25/18 (2013.01); H01L 2224/06102 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48148 (2013.01); H01L 2224/48158 (2013.01); H01L 2224/49107 (2013.01); H01L 2224/49109 (2013.01); H01L 2224/49112 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1435 (2013.01); H01L 2924/182 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate;
a semiconductor chip on the package substrate;
a plurality of first conductive connections connecting the semiconductor chip to the package substrate;
a first spacer and a second spacer on the package substrate, each of the first spacer and the second spacer horizontally spaced apart from the semiconductor chip;
a first tower and a second tower each including a plurality of memory chips, a first memory chip disposed at a lowermost end of the first tower and vertically overlapping the semiconductor chip and the first spacer from a top-down view, and a second memory chip disposed at a lowermost end of the second tower and vertically overlapping the semiconductor chip and the second spacer from a top-down view; and
a plurality of first adhesive layers including an adhesive layer covering a lower surface of the first memory chip and partially covering an upper surface of the semiconductor chip and an adhesive layer covering a lower surface of the second memory chip and partially covering the upper surface of the semiconductor chip.