US 11,791,297 B2
Molded semiconductor package and related methods
Sw Wang, Seremban (MY); Ch Chew, Seremban (MY); Eiji Kurose, Oizumi-machi (JP); and How Kiat Liew, Bukit Jalil (MY)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Feb. 4, 2022, as Appl. No. 17/649,943.
Application 17/649,943 is a division of application No. 15/679,666, filed on Aug. 17, 2017, granted, now 11,244,918.
Prior Publication US 2022/0157756 A1, May 19, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01)
CPC H01L 24/14 (2013.01) [H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 23/3114 (2013.01); H01L 24/96 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01029 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side;
one or more bumps comprised on the first side of the semiconductor die, the one or more bumps comprising a first layer and a second layer directly coupled to the first layer, wherein the first layer comprises a thickness of 10 microns and the second layer comprises a thickness of 20 microns; and
a mold compound encapsulating the semiconductor die on all sides of the semiconductor die, wherein a face of the one or more bumps is exposed through the mold compound;
wherein the first layer is directly coupled to the first side of the semiconductor die.