US 11,791,284 B2
Semiconductor device manufacturing method
Naoko Tsuji, Tokyo (JP); Akira Yamakawa, Tokyo (JP); and Katsuhiko Sumita, Tokyo (JP)
Assigned to Daicel Corporation, Tokyo (JP)
Appl. No. 17/286,712
Filed by DAICEL CORPORATION, Osaka (JP)
PCT Filed Oct. 18, 2019, PCT No. PCT/JP2019/041189
§ 371(c)(1), (2) Date Apr. 19, 2021,
PCT Pub. No. WO2020/085251, PCT Pub. Date Apr. 30, 2020.
Claims priority of application No. 2018-199009 (JP), filed on Oct. 23, 2018.
Prior Publication US 2021/0358867 A1, Nov. 18, 2021
Int. Cl. H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/80 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/8385 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/0715 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
preparing a plurality of first wafer laminates, each of the first wafer laminates having a laminate configuration, in which a first wafer and a second wafer are included, the first wafer having an element forming surface and a back surface opposite from the element forming surface, and the second wafer having an element forming surface and a back surface opposite from the element forming surface, and the element forming surface sides of the first and second wafers are bonded to each other;
performing thickness reduction, at least twice, to the first wafer of each of the first wafer laminates to form first wafer laminates each having the thinned first wafer; and
bonding the thinned first wafer sides of two first wafer laminates having undergone the thickness reduction to each other to form a second wafer laminate.