US 11,791,271 B2
Monolithic formation of a set of interconnects below active devices
Daniel Chanemougame, Albany, NY (US); Lars Liebmann, Albany, NY (US); and Jeffrey Smith, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on May 3, 2021, as Appl. No. 17/306,331.
Claims priority of provisional application 63/085,578, filed on Sep. 30, 2020.
Prior Publication US 2022/0102277 A1, Mar. 31, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 27/092 (2006.01)
CPC H01L 23/5383 (2013.01) [H01L 21/4885 (2013.01); H01L 27/0924 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A system comprising a monolithic substrate comprising:
a first wiring structure formed fully within bulk material of a semiconductor wafer, wherein the first wiring structure comprises a layer of patterned metal fully within the bulk material of the semiconductor wafer with air gaps above the patterned metal;
one or more active devices formed in an epitaxially grown semiconductor material above the first wiring structure; and
a second wiring structure formed above the one or more active devices.