US 11,791,257 B2
Device terminal interconnect structures
Sairam Subramanian, Portland, OR (US); and Walid M. Hafez, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 27, 2021, as Appl. No. 17/562,925.
Application 17/562,925 is a continuation of application No. 15/940,531, filed on Mar. 29, 2018, granted, now 11,227,829.
Prior Publication US 2022/0122911 A1, Apr. 21, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76819 (2013.01); H01L 21/76837 (2013.01); H01L 21/76885 (2013.01); H01L 21/823475 (2013.01); H01L 27/088 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a transistor structure;
a first interconnect feature electrically coupled to the transistor structure, wherein:
the first interconnect feature is over the transistor structure;
a first portion of the first interconnect feature has a first thickness; and
a second portion of the first interconnect feature has a second thickness, less than the first thickness;
a dielectric material adjacent to a sidewall of the first portion of the first interconnect feature, and over the second portion of the first interconnect feature; and
a second interconnect feature in contact with the first portion of the first interconnect feature.