US 11,791,247 B2
Concealed gate terminal semiconductor packages and related methods
Erwin Ian Vamenta Almagro, Lapu-Lapu (PH); Maria Clemens Ypil Quinones, Cebu (PH); Romel N. Manatad, Liloan (PH); Maria Cristina Estacio, Lapu-Lapu (PH); and Elsie Agdon Cabahug, Consolacion (PH)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Jul. 7, 2021, as Appl. No. 17/305,396.
Claims priority of provisional application 63/085,770, filed on Sep. 30, 2020.
Prior Publication US 2022/0102248 A1, Mar. 31, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/49541 (2013.01) [H01L 23/31 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a lead frame;
one or more semiconductor die coupled with the lead frame; and
an interposer coupled with the lead frame and with at least one of the one or more semiconductor die;
wherein the interposer comprises an electrically conductive material on a first side of the interposer and an electrically insulative material on a second side of the interposer;
wherein the interposer is coupled with the lead frame through the electrically insulative material such that the electrically conductive material is electrically isolated from the lead frame; and
wherein the electrically conductive material forms at least two separated contact pads.