US 11,791,230 B2
Fan-out semiconductor package
Joonsung Kim, Suwon-si (KR); Doohwan Lee, Suwon-si (KR); and Jinseon Park, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 23, 2021, as Appl. No. 17/409,281.
Application 17/409,281 is a continuation of application No. 16/681,320, filed on Nov. 12, 2019, granted, now 11,127,646.
Claims priority of application No. 10-2018-0141648 (KR), filed on Nov. 16, 2018.
Prior Publication US 2021/0384095 A1, Dec. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/31 (2006.01); H01L 25/13 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/552 (2006.01); H01L 25/10 (2006.01); H01L 23/522 (2006.01); H01L 23/13 (2006.01)
CPC H01L 23/3128 (2013.01) [H01L 23/13 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/08 (2013.01); H01L 2224/08235 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a fan-out semiconductor package, the method comprising:
forming a frame having a through-hole and including one or more wiring layers;
forming a semiconductor chip in the through-hole of the frame;
forming an encapsulant covering an upper surface of each of the frame and the semiconductor chip, and filling a space between a wall surface of the through-hole of the frame and a side surface of the semiconductor chip;
forming a connection structure below each of the frame and the semiconductor chip, and including one or more redistribution layers;
forming a first metal pattern layer on an upper surface of the encapsulant;
forming an insulating material on the upper surface of the encapsulant and covering the first metal pattern layer; and
forming a second metal pattern layer on an upper surface of the insulating material, a first metal via passing through the insulating material, and a second metal via passing through the insulating material and the encapsulant,
wherein the first metal via electrically connects the first metal pattern layer and the second metal pattern layer, and
wherein the second metal via electrically connects the second metal pattern layer and an uppermost wiring layer among the one or more wiring layers of the frame.