	US 11,791,161 B2
	Pattern fidelity enhancement
Yu-Tien Shen, Tainan (TW); Ya-Wen Yeh, Taipei (TW); Wei-Liang Lin, Hsin-Chu (TW); Ya Hui Chang, Hsinchu (TW); Yung-Sung Yen, New Taipei (TW); Wei-Hao Wu, Hsinchu (TW); Li-Te Lin, Hsinchu (TW); Ru-Gun Liu, Hsinchu County (TW); and Kuei-Shun Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Dec. 7, 2020, as Appl. No. 17/114,070.
Application 17/114,070 is a division of application No. 15/689,172, filed on Aug. 29, 2017, granted, now 10,861,698.
Prior Publication US 2021/0118674 A1, Apr. 22, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G03F 7/09 (2006.01); H01L 21/027 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 21/306 (2006.01); G03F 7/20 (2006.01); G03F 7/11 (2006.01)

CPC H01L 21/0273 (2013.01) [G03F 7/09 (2013.01); H01L 21/0337 (2013.01); H01L 21/311 (2013.01); G03F 7/11 (2013.01); G03F 7/20 (2013.01); H01L 21/0274 (2013.01); H01L 21/306 (2013.01)]

20 Claims

1. A method, comprising:

providing a substrate and a patterning layer over the substrate, wherein the substrate includes a plurality of features to receive a treatment process;

forming a plurality of openings in the patterning layer, wherein the openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer, wherein each of the openings is free of concave corners;

performing an opening expanding process to enlarge each of the openings in the patterning layer, such that the openings in the patterning layer fully overlap with the features from the top view; and

performing a treatment process to the features through the openings.