US 11,791,004 B2
Threshold voltage offset bin selection based on die family in memory devices
Michael Sheperek, Longmont, CO (US); Bruce A. Liikanen, Berthoud, CO (US); Steve Kientz, Westminster, CO (US); Anita Ekren, Loveland, CO (US); and Gerald Cadloni, Longmont, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 14, 2022, as Appl. No. 18/81,004.
Application 18/081,004 is a continuation of application No. 17/070,526, filed on Oct. 14, 2020, granted, now 11,545,227.
Prior Publication US 2023/0115960 A1, Apr. 13, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 7/04 (2006.01); G11C 16/32 (2006.01); G11C 16/30 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/349 (2013.01) [G11C 7/04 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
associating, by a processing device, a set of dies of a block family with a die family, wherein the block family is associated with a first threshold voltage offset bin for voltage offsets to be applied in a read operation; and
responsive to detecting a triggering event, associating each die of the set of dies with a second threshold voltage offset bin for voltage offsets to be applied in a read operation, wherein the second threshold voltage offset bin is selected based on a representative die of the set of dies associated with the die family.