US 11,791,003 B2
Distributed compaction of logical states to reduce program time
Kalyan Chakravarthy Kavalipurapu, Hyderabad (IN); George Matamis, Eagle, ID (US); Yingda Dong, Los Altos, CA (US); and Chang H. Siau, Saratoga, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 5, 2022, as Appl. No. 17/960,252.
Application 17/960,252 is a continuation of application No. 17/247,435, filed on Dec. 10, 2020, granted, now 11,488,677.
Prior Publication US 2023/0022858 A1, Jan. 26, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/3481 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising memory cells; and
control logic, operatively coupled with the memory array, the control logic to perform operations comprising:
causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states;
causing the memory cells to be programmed with a compacted subsequent voltage distribution representing an encoded compression of a subset of the multiple logical states, wherein the compacted subsequent voltage distribution is to span between a program verify voltage level of the subset and a next-higher program verify voltage level of the multiple logical states that is above the program verify voltage level; and
causing a first program verify operation of the compacted subsequent voltage distribution to be performed on the memory cells at the program verify voltage level.