CPC G11C 16/3481 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory array comprising memory cells; and
control logic, operatively coupled with the memory array, the control logic to perform operations comprising:
causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states;
causing the memory cells to be programmed with a compacted subsequent voltage distribution representing an encoded compression of a subset of the multiple logical states, wherein the compacted subsequent voltage distribution is to span between a program verify voltage level of the subset and a next-higher program verify voltage level of the multiple logical states that is above the program verify voltage level; and
causing a first program verify operation of the compacted subsequent voltage distribution to be performed on the memory cells at the program verify voltage level.
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