US 11,790,999 B2
Resistive random access memory erase techniques and apparatus
Jeremy Guy, San Jose, CA (US); Sung Hyun Jo, Sunnyvale, CA (US); Hagop Nazarian, San Jose, CA (US); Ruchirkumar Shah, San Jose, CA (US); and Liang Zhao, Santa Clara, CA (US)
Assigned to CROSSBAR, INC., Santa Clara, CA (US)
Filed by CROSSBAR, INC., Santa Clara, CA (US)
Filed on Apr. 27, 2021, as Appl. No. 17/242,015.
Application 17/242,015 is a continuation of application No. 16/291,467, filed on Mar. 4, 2019, granted, now 10,998,064.
Claims priority of provisional application 62/638,526, filed on Mar. 5, 2018.
Prior Publication US 2021/0312995 A1, Oct. 7, 2021
Int. Cl. G11C 16/34 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 11/5678 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for erasing a plurality of two-terminal memory cells, comprising:
applying a first erase process to a plurality of two-terminal memory cells of a device;
applying a first read process to the plurality of two-terminal memory cells and verifying the plurality of two-terminal memory cells are in an unprogrammed state;
applying a weak program process to the plurality of two-terminal memory cells;
applying a second read process to determine whether a memory cell of the plurality of two-terminal memory cells is in a programmed state in response to the weak program process; and
applying a second erase process to the memory cell in response to determining that the memory cell is in the programmed state.