US 11,790,998 B2
Eliminating write disturb for system metadata in a memory sub-system
Tingjun Xie, Milpitas, CA (US); Zhenming Zhou, San Jose, CA (US); Zhenlei Shen, Milpitas, CA (US); and Charles See Yeung Kwong, Redwood City, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 25, 2021, as Appl. No. 17/411,278.
Prior Publication US 2023/0067639 A1, Mar. 2, 2023
Int. Cl. G11C 11/34 (2006.01); G11C 16/34 (2006.01); G11C 16/24 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3418 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
identifying a plurality of memory units residing in a first location of the memory device, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device;
determining that a write disturb capability associated with the first location of the memory device satisfies a threshold criterion; and
responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, remapping a plurality of logical addresses associated with the plurality of memory units to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.