CPC G11C 16/3418 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] | 20 Claims |
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
identifying a plurality of memory units residing in a first location of the memory device, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device;
determining that a write disturb capability associated with the first location of the memory device satisfies a threshold criterion; and
responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, remapping a plurality of logical addresses associated with the plurality of memory units to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.
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