CPC G11C 16/14 (2013.01) [G11C 16/0483 (2013.01); H01L 29/735 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a plurality of memory cells;
a source plate electrically coupled to the plurality of memory cells; and
a discharge circuit including a bipolar junction transistor device electrically coupled to the source plate,
wherein the bipolar junction transistor device is configured to drop a voltage at the source plate by discharging current through the bipolar junction transistor device.
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