| CPC G11C 11/412 (2013.01) [G06N 3/08 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01)] | 13 Claims |
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1. An electronic device comprising:
a first column including:
a first memory cell configured to output first result data of a logical value determined according to a logical operation through a first bit line or a second bit line, based on first input data input through a first word line and a first weight, including a first transistor configured to receive a first voltage through the first word line and connected between a first node and the first bit line and a second transistor configured to receive a second voltage through a second word line and connected between a second node and the second bit line, and
a second memory cell configured to output second result data of a logical value determined according to the logical operation through the first bit line or the second bit line, based on second input data input through a third word line and a second weight, including a third transistor configured to receive a third voltage through the third word line and connected between a third node and the first bit line and a fourth transistor configured to receive a fourth voltage through a fourth word line and connected between a fourth node and the second bit line; and
an amplification circuit configured to output a sum of the first result data and the second result data.
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