US 11,790,978 B2
Register file with write pre-charge
Bassel Daher, Nazareth (IL); Ari-Shaul Leibman, Talmey Elazar (IL); George Shchupak, Zviya (IL); and Or O Rotem, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2019, as Appl. No. 16/578,992.
Prior Publication US 2021/0090635 A1, Mar. 25, 2021
Int. Cl. G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/413 (2006.01); G11C 7/22 (2006.01)
CPC G11C 11/4085 (2013.01) [G11C 7/222 (2013.01); G11C 11/4074 (2013.01); G11C 11/413 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a shared shunt device coupled to a voltage rail to provide a shared voltage line;
at least two memory bit cells coupled to the shared voltage line; and
a transmission gate coupled between the voltage rail and the shared voltage line, wherein the transmission gate is controlled by a write pre-charge clock to pre-charge the shared voltage line for a write operation to one of the at least two memory bit cells while the shunt device is providing the shared voltage line.