CPC G11C 11/4085 (2013.01) [G11C 7/222 (2013.01); G11C 11/4074 (2013.01); G11C 11/413 (2013.01)] | 14 Claims |
1. An apparatus comprising:
a shared shunt device coupled to a voltage rail to provide a shared voltage line;
at least two memory bit cells coupled to the shared voltage line; and
a transmission gate coupled between the voltage rail and the shared voltage line, wherein the transmission gate is controlled by a write pre-charge clock to pre-charge the shared voltage line for a write operation to one of the at least two memory bit cells while the shunt device is providing the shared voltage line.
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