CPC G11C 11/40615 (2013.01) [G11C 7/04 (2013.01); G11C 11/4076 (2013.01); G11C 11/40622 (2013.01)] | 20 Claims |
1. A memory controller comprising:
a security level setting circuit suitable for setting a security level by monitoring a risk of a row hammer attack; and
a refresh management command control circuit suitable for controlling the number of times that a refresh management command is to be applied to a memory per unit time according to the security level.
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