CPC G11C 7/222 (2013.01) [G06F 12/0811 (2013.01); G06F 13/1668 (2013.01); G11C 5/14 (2013.01); G11C 7/1045 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01)] | 20 Claims |
15. An electronic device comprising:
a system-on-chip (SoC) including a processor, a first memory controller controlled by the processor, and a second memory controller controlled by the processor;
a first memory device including a first memory channel configured to operate in a first cache mode and communicate with the first memory controller, and a second memory channel configured to operate in a first memory mode and communicate with the first memory controller; and
a second memory device configured to communicate with the second memory controller,
wherein the first memory channel is further configured to, based on a command from the first memory controller, change an operation mode from the first cache mode to the first memory mode.
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