US 11,790,963 B2
Electronic device including near-memory supporting mode setting, and method of operating the same
Ki-Seok Oh, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 30, 2022, as Appl. No. 17/708,414.
Claims priority of application No. 10-2021-0102389 (KR), filed on Aug. 4, 2021.
Prior Publication US 2023/0044654 A1, Feb. 9, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01); G06F 13/16 (2006.01); G11C 5/14 (2006.01); G06F 12/0811 (2016.01)
CPC G11C 7/222 (2013.01) [G06F 12/0811 (2013.01); G06F 13/1668 (2013.01); G11C 5/14 (2013.01); G11C 7/1045 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01)] 20 Claims
OG exemplary drawing
 
15. An electronic device comprising:
a system-on-chip (SoC) including a processor, a first memory controller controlled by the processor, and a second memory controller controlled by the processor;
a first memory device including a first memory channel configured to operate in a first cache mode and communicate with the first memory controller, and a second memory channel configured to operate in a first memory mode and communicate with the first memory controller; and
a second memory device configured to communicate with the second memory controller,
wherein the first memory channel is further configured to, based on a command from the first memory controller, change an operation mode from the first cache mode to the first memory mode.