CPC G11C 7/222 (2013.01) [G06F 13/1689 (2013.01); G11C 7/02 (2013.01); G11C 7/22 (2013.01)] | 20 Claims |
1. A memory controller, comprising:
an interface to receive a data strobe signal and corresponding read data, wherein the data strobe signal and the read data correspond to a read command issued by the memory controller, and wherein the read data is received in accordance with the data strobe signal;
data receive circuitry, including gate logic to gate the data strobe signal with an internally generated data strobe enable signal to generate a clean data strobe signal, and data capture logic responsive to the clean data strobe signal to capture the read data;
burst error detection circuitry to generate a burst error signal indicating whether a count of edges of the clean data strobe signal during a memory read is equal to a predefined value; and
data strobe adjust circuitry to adjust timing of the internally generated data strobe enable signal in accordance with a value of the burst error signal.
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