US 11,790,867 B2
Active matrix substrate, liquid crystal display device, and organic EL display device
Tetsuo Kikuchi, Sakai (JP); Hideki Kitagawa, Sakai (JP); Hajime Imai, Sakai (JP); Toshikatsu Itoh, Sakai (JP); Masahiko Suzuki, Sakai (JP); Teruyuki Ueda, Sakai (JP); Kengo Hara, Sakai (JP); Setsuji Nishimiya, Sakai (JP); and Tohru Daitoh, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Filed by Sharp Kabushiki Kaisha, Sakai (JP)
Filed on Dec. 7, 2022, as Appl. No. 18/76,433.
Application 18/076,433 is a continuation of application No. 17/724,781, filed on Apr. 20, 2022, granted, now 11,551,629.
Application 17/724,781 is a continuation of application No. 17/401,396, filed on Aug. 13, 2021, granted, now 11,322,105, issued on May 3, 2022.
Application 17/401,396 is a continuation of application No. 16/495,463, granted, now 11,107,429, issued on Aug. 31, 2021, previously published as PCT/JP2018/010524, filed on Mar. 16, 2018.
Claims priority of application No. 2017-060482 (JP), filed on Mar. 27, 2017.
Prior Publication US 2023/0100273 A1, Mar. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/36 (2006.01); G02F 1/1362 (2006.01); H10K 59/00 (2023.01); H10K 59/123 (2023.01); H01L 27/12 (2006.01)
CPC G09G 3/3648 (2013.01) [G02F 1/136213 (2013.01); H10K 59/00 (2023.02); H10K 59/123 (2023.02); H01L 27/1214 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An active matrix substrate including a display region and a peripheral region, the display region being defined by pixel regions arranged in a matrix, the peripheral region being located around the display region, the active matrix substrate comprising:
a substrate;
a first insulating layer;
a second insulating layer provided above the first insulating layer;
a first Thin Film Transistor (TFT);
a second TFT disposed in the display region; wherein the first TFT includes:
a silicon semiconductor layer including a first channel region, a first source region, and a first drain region;
a first gate insulating layer being provided above the silicon semiconductor layer;
a first gate electrode being provided above the first gate insulating layer, the first gate electrode opposing the first channel region with the first gate insulating layer therebetween; and
a first electrode being electrically connected to one of the first source region and the first drain region;
the second TFT includes:
an oxide semiconductor layer including a second channel region, a second source region, and a second drain region;
a second gate insulating layer being provided above the oxide semiconductor layer;
a second gate electrode being provided above the second gate insulating layer, the second gate electrode opposing the second channel region with the second gate insulating layer therebetween; and
a second electrode being electrically connected to one of the second source region and the second drain region;
the first insulating layer includes the first gate insulating layer;
the second insulating layer includes a portion that covers the first gate electrode and the second gate electrode;
the first electrode and the second electrode are provided above the second insulating layer;
the first electrode is electrically connected to the one of the first source region and the first drain region via a first contact hole defined in the first insulating layer and the second insulating layer; and
the second electrode is electrically connected to the one of the second source region and the second drain region via a second contact hole defined in the second insulating layer.