CPC G06Q 20/40145 (2013.01) [G06F 21/31 (2013.01); G06F 21/32 (2013.01); G06Q 20/204 (2013.01); G06Q 20/3278 (2013.01); G06Q 20/382 (2013.01); G06Q 20/4014 (2013.01); H04L 9/3231 (2013.01); H04W 12/065 (2021.01); H04W 12/068 (2021.01)] | 19 Claims |
1. A multi-user device, comprising:
a secure processor circuit;
a secure element comprising a first processor and a first memory, wherein the first memory stores program instructions that when executed by the first processor cause the first processor to perform:
storing, in the first memory, payment information associated with a plurality of users;
receiving a first payment request to communicate the payment information associated with a first user of the plurality of users;
sending a request to perform an authentication of the first user to the secure processor circuit;
communicating the payment information associated with the first user in response to the authenticating of the first user; and
the secure processor circuit comprising a second processor and a second memory, wherein the second memory stores program instructions that when executed by the second processor cause the second processor to perform:
authenticating the first user in response to the request from the secure element.
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