CPC G06N 3/08 (2013.01) [G06N 3/04 (2013.01); H03M 7/30 (2013.01)] | 20 Claims |
1. A neural network deep learning data control apparatus comprising:
a memory;
an encoding circuit configured to
receive a data sequence,
generate a compressed data sequence by compressing consecutive bits having the same bit value in a bit string of the data sequence are compressed into a single bit of the compressed data sequence,
generate a data discrimination sequence discriminating a data repetition bit and an invalid bit in a bit string of the compressed data sequence, and
write the compressed data sequence and the data discrimination sequence to the memory; and
a decoding circuit configured to
read the compressed data sequence and the data discrimination sequence from the memory, and
determine a bit in the bit string of the compressed data sequence set for transmission to a neural network circuit, based on the data discrimination sequence.
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