US 11,790,217 B2
LSTM circuit with selective input computation
Ram Krishnamurthy, Portland, OR (US); Gregory K. Chen, Portland, OR (US); Raghavan Kumar, Hillsboro, OR (US); Phil Knag, Hillsboro, OR (US); and Huseyin Ekin Sumbul, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2019, as Appl. No. 16/583,201.
Prior Publication US 2020/0019846 A1, Jan. 16, 2020
Int. Cl. G06N 3/063 (2023.01); G06F 7/523 (2006.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 7/509 (2006.01); G06F 7/544 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 7/5095 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 9/30098 (2013.01); G06F 9/3893 (2013.01)] 20 Claims
OG exemplary drawing
 
11. A computing system, comprising:
a plurality of processing cores;
a network interface;
a main memory;
a main memory controlled coupled between the main memory and the plurality of processing cores; and,
a long short term memory (LSTM) circuit comprising a multiply accumulate circuit (MAC) having a multiplier circuit and an accumulator circuit, the LSTM circuit further comprising selection circuitry and a storage element, the selection circuitry to select a stored product term and the multiplier circuit to avoid explicit multiplication of a product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold, the storage element to store the stored product term.