US 11,790,208 B2
Output circuitry for non-volatile memory array in neural network
Farnood Merrikh Bayat, Goleta, CA (US); Xinjie Guo, Goleta, CA (US); Dmitri Strukov, Goleta, CA (US); Nhan Do, Saratoga, CA (US); Hieu Van Tran, San Jose, CA (US); Vipin Tiwari, Dublin, CA (US); and Mark Reiten, Alamo, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US); and The Regents of the University of California, Oakland, CA (US)
Filed on Apr. 22, 2021, as Appl. No. 17/238,077.
Application 17/238,077 is a continuation of application No. 15/594,439, filed on May 12, 2017, granted, now 11,308,383.
Claims priority of provisional application 62/337,760, filed on May 17, 2016.
Prior Publication US 2021/0287065 A1, Sep. 16, 2021
Int. Cl. G06N 3/04 (2023.01); G11C 11/54 (2006.01); G06N 3/063 (2023.01); G11C 16/34 (2006.01); G11C 29/38 (2006.01); G06N 3/045 (2023.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); G11C 16/16 (2006.01); G06F 3/06 (2006.01)
CPC G06N 3/04 (2013.01) [G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G11C 11/54 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/3436 (2013.01); G11C 29/38 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory system, comprising:
an array of non-volatile memory cells arranged into rows and columns, respective non-volatile memory cells comprising a word line terminal, a source line terminal, and a bit line terminal;
a plurality of source lines, respective source lines coupled to source line terminals of non-volatile memory cells in a respective row of the array;
a plurality of bit lines, respective bit lines coupled to bit line terminals of non-volatile memory cells in a respective column of the array; and
a plurality of word lines, wherein at least one of the plurality of word lines is coupled to word line terminals of non-volatile memory cells in a first row of the array and word line terminals of non-volatile memory cells in a second row of the array, wherein the first row and the second row are different rows in the array and the first row is not adjacent to the second row.