CPC G06N 3/04 (2013.01) [G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G11C 11/54 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/3436 (2013.01); G11C 29/38 (2013.01)] | 17 Claims |
1. A memory system, comprising:
an array of non-volatile memory cells arranged into rows and columns, respective non-volatile memory cells comprising a word line terminal, a source line terminal, and a bit line terminal;
a plurality of source lines, respective source lines coupled to source line terminals of non-volatile memory cells in a respective row of the array;
a plurality of bit lines, respective bit lines coupled to bit line terminals of non-volatile memory cells in a respective column of the array; and
a plurality of word lines, wherein at least one of the plurality of word lines is coupled to word line terminals of non-volatile memory cells in a first row of the array and word line terminals of non-volatile memory cells in a second row of the array, wherein the first row and the second row are different rows in the array and the first row is not adjacent to the second row.
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