US 11,790,151 B2
System for generating layout diagram including wiring arrangement
Fong-Yuan Chang, Hsinchu (TW); Chin-Chou Liu, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Meng-Kai Hsu, Hsinchu (TW); Pin-Dai Sue, Hsinchu (TW); Po-Hsiang Huang, Hsinchu (TW); Yi-Kan Cheng, Hsinchu (TW); Chi-Yu Lu, Hsinchu (TW); and Jung-Chou Tsai, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 10, 2022, as Appl. No. 17/885,106.
Application 17/885,106 is a division of application No. 16/299,973, filed on Mar. 12, 2019.
Claims priority of provisional application 62/644,306, filed on Mar. 16, 2018.
Prior Publication US 2022/0382957 A1, Dec. 1, 2022
Int. Cl. G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium, the system comprising:
at least one processor; and
at least one memory including computer program code for one or more programs;
wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute generating the layout diagram including:
placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer;
determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and
temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.