CPC G06F 30/327 (2020.01) [G06F 30/337 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2119/02 (2020.01); G06F 2119/10 (2020.01)] | 17 Claims |
1. A method of making an integrated circuit, the method comprising:
for each pair of connected logic stages possible for use in the integrated circuit, determining a static noise margin (SNM) for the pair of connected logic stages with a metallic carbon nanotube (m-CNT), the SNM representing an immunity to noise of the pair of logic stages when made with the m-CNT and accounting for a likelihood that either or both logic gates of the pair of connected logic gates include a m-CNT; and
making the integrated circuit with only those pairs of connected logic stages having an SNM above a threshold SNM despite the possible presence of the m-CNT in each pair of those pairs of connected logic gates.
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