US 11,790,141 B2
Systems and methods for designing integrated circuits
Gage Krieger Hills, Mill Valley, CA (US); and Max Shulaker, Weston, MA (US)
Assigned to Massachusetts Institute of Technology, Cambridge, MA (US)
Filed by Massachusetts Institute of Technology, Cambridge, MA (US)
Filed on Jun. 2, 2021, as Appl. No. 17/336,916.
Application 17/336,916 is a division of application No. 16/565,634, filed on Sep. 10, 2019, granted, now 11,062,067.
Claims priority of provisional application 62/729,056, filed on Sep. 10, 2018.
Prior Publication US 2021/0294959 A1, Sep. 23, 2021
Int. Cl. G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/337 (2020.01); G06F 111/04 (2020.01); G06F 119/10 (2020.01); G06F 119/02 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/337 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2119/02 (2020.01); G06F 2119/10 (2020.01)] 17 Claims
OG exemplary drawing
 
1. A method of making an integrated circuit, the method comprising:
for each pair of connected logic stages possible for use in the integrated circuit, determining a static noise margin (SNM) for the pair of connected logic stages with a metallic carbon nanotube (m-CNT), the SNM representing an immunity to noise of the pair of logic stages when made with the m-CNT and accounting for a likelihood that either or both logic gates of the pair of connected logic gates include a m-CNT; and
making the integrated circuit with only those pairs of connected logic stages having an SNM above a threshold SNM despite the possible presence of the m-CNT in each pair of those pairs of connected logic gates.