US 11,790,127 B1
Full correlation aging analysis over combined process voltage temperature variation
Donald John Oriordan, Sunnyvale, CA (US)
Assigned to Synopsys, Inc., Mountain View, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on May 11, 2020, as Appl. No. 16/872,075.
Claims priority of provisional application 62/846,651, filed on May 11, 2019.
Int. Cl. G06F 30/20 (2020.01); G06F 30/39 (2020.01); G06F 119/08 (2020.01); G06F 119/02 (2020.01); G06F 119/04 (2020.01)
CPC G06F 30/20 (2020.01) [G06F 30/39 (2020.01); G06F 2119/02 (2020.01); G06F 2119/04 (2020.01); G06F 2119/08 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
obtaining, by a processing device, device-level parameter degradation data for at least one process, voltage, temperature (PVT) condition associated with a multi-dimensional PVT space by extrapolating device-level stress data of a circuit comprising one or more devices to a target circuit age for the circuit;
obtaining, by the processing device, an aged circuit comprising the one or more devices by applying the device-level parameter degradation data to a set of device-level parameters; and
initiating, by the processing device, a process to perform a plurality of degradation simulations with respect to the aged circuit for a process corner associated with the at least one PVT condition, wherein each degradation simulation of the plurality of degradation simulations is performed for a respective set of sweep parameters of a plurality of sets of sweep parameters, and wherein each set of sweep parameters of the plurality of sets of sweep parameters corresponds to a respective dimension of the multi-dimensional PVT space.