US 11,789,896 B2
Processor for configurable parallel computations
Wensheng Hua, Fremont, CA (US)
Assigned to STAR ALLY INTERNATIONAL LIMITED, Tortola, VI (US)
Filed by STAR ALLY INTERNATIONAL LIMITED, Tortola (VG)
Filed on Dec. 23, 2020, as Appl. No. 17/132,437.
Claims priority of provisional application 62/954,952, filed on Dec. 30, 2019.
Prior Publication US 2021/0200710 A1, Jul. 1, 2021
Int. Cl. G06F 15/78 (2006.01); G06F 13/12 (2006.01)
CPC G06F 15/7871 (2013.01) [G06F 13/124 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A processor receiving a system input data stream, the processor being included in a system that further comprises a host processor, the processor comprising:
a first plurality of stream processors and a second plurality of stream processors, each stream processor being configurable by the host processor to receive an input data stream and to provide an output data stream, wherein the input data stream of a selected one of the stream processors comprises the system input data stream, and wherein each stream processor comprises an instruction memory, a plurality of arithmetic logic circuits, and a control processor that executes a configurable sequence of instructions stored in the instruction memory to control operations in the arithmetic logic circuits;
a first plurality of configurable interconnection circuits, a second plurality of configurable interconnection circuits, and a third plurality of interconnection circuits, wherein (i) each configurable interconnection circuit in the first plurality of configurable interconnection circuits is configurable by both the host processor and one of the control processors in the first plurality of stream processors to route the output data stream of one of the plurality of stream processors as the input data stream of another one of the first plurality of stream processors, (ii) each configurable interconnection circuit in the second plurality of configurable interconnection circuits is configurable by both the host processor and one of the control processors in the second plurality of stream processors to route the output data stream of one of the plurality of stream processors as the input data stream of another one of the second plurality of stream processors; and wherein (iii) each configurable interconnection circuit in the second plurality of configurable interconnection circuits is configurable by the host processor to route one of the output data streams of the first plurality of stream processors, through the first and second pluralities of interconnection circuits, as one of the input data streams of the second plurality of stream processors; and
a global bus providing access to and being accessible by the stream processors and the configurable interconnection circuits.