US 11,789,893 B2
Memory system, memory controller and memory chip
Chun Shiah, Hsinchu (TW)
Assigned to ETRON TECHNOLOGY, INC., Hsinchu (TW)
Filed by ETRON TECHNOLOGY, INC., Hsinchu (TW)
Filed on Aug. 2, 2021, as Appl. No. 17/391,755.
Claims priority of provisional application 63/061,194, filed on Aug. 5, 2020.
Prior Publication US 2022/0156223 A1, May 19, 2022
Int. Cl. G06F 13/42 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/4291 (2013.01) [G06F 13/1678 (2013.01); G06F 13/1689 (2013.01); G06F 13/423 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory system comprising:
a controller;
a memory comprising a data bus configured to receive a parallel command, and a serial bus configured to receive a serial command; and
a physical layer circuit configured to transmit the parallel command to the data bus, the physical layer circuit coupled between the memory and the controller;
wherein the physical layer circuit is configured to convert an input parallel strobe (STB) data into the serial command and transmit the serial command to the serial bus; and the physical layer circuit includes at-least-one-level switch circuit for converting the input parallel strobe (STB) data into the serial command, and the serial bus is a single strobe pin.