CPC G06F 13/4291 (2013.01) [G06F 13/1678 (2013.01); G06F 13/1689 (2013.01); G06F 13/423 (2013.01)] | 12 Claims |
1. A memory system comprising:
a controller;
a memory comprising a data bus configured to receive a parallel command, and a serial bus configured to receive a serial command; and
a physical layer circuit configured to transmit the parallel command to the data bus, the physical layer circuit coupled between the memory and the controller;
wherein the physical layer circuit is configured to convert an input parallel strobe (STB) data into the serial command and transmit the serial command to the serial bus; and the physical layer circuit includes at-least-one-level switch circuit for converting the input parallel strobe (STB) data into the serial command, and the serial bus is a single strobe pin.
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