US 11,789,892 B2
Recalibration of PHY circuitry for the PCI express (PIPE) interface based on using a message bus interface
Michelle C. Jen, Mountain View, CA (US); Minxi Gao, Chandler, AZ (US); Debendra Das Sharma, Saratoga, CA (US); Fulvio Spagna, San Jose, CA (US); Bruce A. Tennant, Hillsboro, OR (US); and Noam Dolev Geldbard, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 6, 2022, as Appl. No. 17/738,625.
Application 17/738,625 is a continuation of application No. 16/926,524, filed on Jul. 10, 2020, granted, now 11,327,920.
Application 16/926,524 is a continuation of application No. 16/446,470, filed on Jun. 19, 2019, granted, now 10,713,209.
Claims priority of provisional application 62/802,946, filed on Feb. 8, 2019.
Prior Publication US 2022/0269641 A1, Aug. 25, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/42 (2006.01)
CPC G06F 13/4282 (2013.01) [G06F 2213/0026 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a request to recalibrate a receiver by a physical layer (PHY) block via a message bus portion of an interface with a media access (MAC) block;
sending an acknowledgment of the request to recalibrate via the message bus portion of the interface;
recalibrating the receiver in response to the request; and
sending a completion message via the message bus portion of the interface after the recalibrating is completed.