CPC G06F 13/4234 (2013.01) [G06F 11/1068 (2013.01); G11C 7/10 (2013.01)] | 21 Claims |
1. An apparatus comprising:
a plurality of memory devices;
memory interface circuitry; and
a parallel bus operably connecting the memory interface circuitry to the plurality of memory devices, the parallel bus including:
a plurality of independent control lines, each of the plurality of independent control lines operably coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices, and
a plurality of independent data channels, each of the plurality of independent data channels operably coupling the memory interface circuitry to a corresponding subset of a plurality of second subsets of the plurality of memory devices,
wherein each of the plurality of first subsets intersects each of the plurality of second subsets, and
wherein each of the second subsets of the plurality of memory devices includes memory devices having different memory types.
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