US 11,789,890 B2
Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities
Thomas H. Kinsley, Boise, ID (US); George E. Pax, Lake City, FL (US); Timothy M. Hollis, Meridian, ID (US); Yogesh Sharma, Boise, ID (US); Randon K. Richards, Kuna, ID (US); Chan H. Yoo, Boise, ID (US); Gregory A. King, Hastings, MN (US); and Eric J. Stave, Meridian, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jun. 27, 2022, as Appl. No. 17/850,927.
Application 17/850,927 is a continuation of application No. 16/720,976, filed on Dec. 19, 2019, granted, now 11,416,437.
Claims priority of provisional application 62/782,276, filed on Dec. 19, 2018.
Prior Publication US 2022/0335000 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/42 (2006.01); G06F 11/10 (2006.01); G11C 7/10 (2006.01)
CPC G06F 13/4234 (2013.01) [G06F 11/1068 (2013.01); G11C 7/10 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of memory devices;
memory interface circuitry; and
a parallel bus operably connecting the memory interface circuitry to the plurality of memory devices, the parallel bus including:
a plurality of independent control lines, each of the plurality of independent control lines operably coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices, and
a plurality of independent data channels, each of the plurality of independent data channels operably coupling the memory interface circuitry to a corresponding subset of a plurality of second subsets of the plurality of memory devices,
wherein each of the plurality of first subsets intersects each of the plurality of second subsets, and
wherein each of the second subsets of the plurality of memory devices includes memory devices having different memory types.