CPC G06F 13/1668 (2013.01) [H04L 25/4917 (2013.01)] | 20 Claims |
1. A memory system, comprising:
a memory controller configured to:
transmit a command or an address to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels, and
transmit data to the first channel based on the data input/output signal having one of two different voltage levels; and
a memory device configured to:
sample the command or the address received via the first channel in a pulse amplitude modulation (PAM)-N mode, and
sample the data received via the first channel in a non return to zero (NRZ) mode.
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