US 11,789,871 B2
Microprocessor that prevents same address load-load ordering violations
John G. Favor, San Francisco, CA (US); and Srivatsan Srinivasan, Cedar Park, TX (US)
Assigned to Ventana Micro Systems Inc., Cupertino, CA (US)
Filed by Ventana Micro Systems Inc., Cupertino, CA (US)
Filed on May 18, 2022, as Appl. No. 17/747,815.
Application 17/747,815 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406.
Application 17/351,927 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686.
Application 17/351,946 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/315,262 is a continuation in part of application No. 17/370,009, filed on Jul. 8, 2021, granted, now 11,481,332.
Application 17/370,009 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406.
Application 17/351,927 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686.
Application 17/351,946 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/351,927 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Application 17/351,946 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400.
Claims priority of provisional application 63/331,487, filed on Apr. 15, 2022.
Claims priority of provisional application 63/271,934, filed on Oct. 26, 2021.
Prior Publication US 2022/0358047 A1, Nov. 10, 2022
Int. Cl. G06F 12/0891 (2016.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 12/0891 (2013.01) [G06F 9/30043 (2013.01); G06F 9/3836 (2013.01)] 31 Claims
OG exemplary drawing
 
1. A microprocessor that prevents same address load-load ordering violations, comprising:
a cache;
a load queue, wherein each entry of the load queue is configured to hold:
a load physical memory line address associated with a load instruction; and
an indication of whether the load instruction has completed execution;
wherein the microprocessor is configured to:
perform a fill of a copy of a line of memory specified by a fill physical memory line address into an entry of the cache;
perform a snoop of the load queue with the fill physical memory line address, wherein the snoop is performed either before the fill or in an atomic manner with the fill, wherein the atomic manner is with respect to ability of the filled entry to be hit upon by any load instruction;
determine, based on the snoop, whether a condition is true, wherein the condition comprises:
the fill physical memory line address matches one or more load physical memory line addresses in one or more entries of the load queue associated with one or more load instructions that have completed execution; and
there are one or more other load instructions in the load queue that have not completed execution; and
if the condition is true, flush at least the one or more other load instructions in the load queue that have not completed execution.