US 11,789,869 B2
Contention tracking for latency reduction of exclusive operations
Anurag Chaudhary, San Jose, CA (US); Christopher Richard Feilbach, Santa Clara, CA (US); Jasjit Singh, San Francisco, CA (US); Manuel Gautho, Truckee, CA (US); Aprajith Thirumalai, Santa Clara, CA (US); and Shailender Chaudhry, Santa Clara, CA (US)
Assigned to Nvidia Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Jan. 20, 2022, as Appl. No. 17/580,360.
Prior Publication US 2023/0244604 A1, Aug. 3, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 12/0837 (2016.01)
CPC G06F 12/0837 (2013.01) [G06F 2212/1032 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory; and
a processing device, operatively coupled with the memory, to perform operations comprising:
determining that a first thread is blocked from accessing data of a plurality of memory locations that are locked;
updating a data structure to indicate that the plurality of memory locations are contentious, wherein the plurality of memory locations remain contentious after being unlocked;
processing, for a second thread, a first memory operation from a queue comprising the first memory operation, a plurality of intervening operations, and a second memory operation, wherein the first memory operation and the second memory operation operate on data of a memory location;
determining, based on the data structure, that the memory location is a contentious memory location; and
processing, for the second thread, the second memory operation before at least one of the intervening operations, wherein the at least one intervening operation was between the first memory operation and the second memory operation in the queue.