US 11,789,865 B2
Semiconductor device
Sang Soo Ko, Yongin-si (KR); Jae Gon Kim, Hwaseong-si (KR); Kyoung Young Kim, Suwon-si (KR); and Sang Hyuck Ha, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 8, 2021, as Appl. No. 17/545,797.
Application 17/545,797 is a continuation of application No. 16/526,452, filed on Jul. 30, 2019, granted, now 11,200,165.
Claims priority of application No. 10-2018-0153279 (KR), filed on Dec. 3, 2018.
Prior Publication US 2022/0100656 A1, Mar. 31, 2022
Int. Cl. G06F 12/0802 (2016.01); G06F 3/06 (2006.01); G06F 13/42 (2006.01); G06N 3/08 (2023.01)
CPC G06F 12/0802 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 13/4282 (2013.01); G06N 3/08 (2013.01); G06F 2212/60 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first processor which is electrically connected to a first memory unit including at least one memory and executes an operation on a training dataset; and
a compiler which generates a scheduling code of a path of data to be moved in an operation process of a training data,
wherein the scheduling code includes information on a first path in which the data is moved between the first processor and the first memory unit, and a second path in which the data is moved between memories included in the first memory unit, and
the first processor executes the operation on the training dataset on a basis of the scheduling code.