CPC G06F 12/0802 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 13/4282 (2013.01); G06N 3/08 (2013.01); G06F 2212/60 (2013.01)] | 11 Claims |
1. A semiconductor device comprising:
a first processor which is electrically connected to a first memory unit including at least one memory and executes an operation on a training dataset; and
a compiler which generates a scheduling code of a path of data to be moved in an operation process of a training data,
wherein the scheduling code includes information on a first path in which the data is moved between the first processor and the first memory unit, and a second path in which the data is moved between memories included in the first memory unit, and
the first processor executes the operation on the training dataset on a basis of the scheduling code.
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